Among conventional PLLs (Phase Locked Loops), there has been a dual loop PLL which includes a frequency comparison loop and a phase comparison loop and which achieves phase synchronization over a wide output frequency range without increasing the gain of a voltage controlled oscillator. This conventional technique is disclosed in, for example, Yi-Cheng Chang, Edwin W. Greeneich, “MONOLITHIC PHASE-LOCKED LOOP CIRCUITS WITH COARSE-STEERING ACQUISITION AID” Circuits and Systems, 1999. 42nd Midwest Symposium on Volume: 1, 1999 Page(s): 283–286 vol. 1.
The dual loop PLL is capable of decreasing the gain of a voltage controlled oscillator even if the output frequency range is expanded. Thus, the dual loop PLL has the advantage of decreasing the influence which is caused by a variation of a voltage input to the voltage controlled oscillator and imposed on the oscillation frequency. Further, the dual loop PLL has the function of autonomously correcting the characteristics of the voltage controlled oscillator to necessary characteristics by a frequency comparison even when the characteristics of the voltage controlled oscillator are varied due to variations in the production process.
FIG. 13 shows a circuit structure of a conventional dual loop PLL. In FIG. 13, reference numeral 1 denotes a phase comparator, reference numeral 2 denotes a charge pump, reference numeral 3 denotes an operation mode switch which switches between the P-side and the F-side, reference numeral 4 denotes a loop filter, reference numeral 5 denotes a voltage controlled oscillator (VCO), reference numeral 6 denotes a frequency divider circuit, reference numeral 7 denotes a frequency comparator, reference numeral 8 denotes an up/down counter, reference numeral 9 denotes a VCO characteristic control circuit, reference numeral 10 denotes external reference clock CLex, reference numeral 11 denotes internal clock CLin, reference numeral 15 denotes reference voltage Vref, reference numeral 16 denotes frequency comparison stop signal FSTOP, and reference mark OUT denotes an output terminal to which the output side of the voltage controlled oscillator 5 is connected.
Hereinafter, an operation of the dual loop PLL is described with reference to FIG. 13.
First, in the dual loop PLL, the operation mode switch 3 is set on the F-side, so that a voltage input to the loop filter 4 is reference voltage Vref (15), and the loop starting from the phase comparator 1 is open. Thus, the loop is a frequency comparison loop which passes through the frequency comparator 7, the up/down counter 8, the VCO characteristic control circuit 9, the voltage controlled oscillator 5 and the frequency divider circuit 6.
In the frequency comparison loop, constant reference voltage Vref (15) is supplied as an input voltage to the voltage controlled oscillator 5. The dual loop PLL operates only in a frequency comparison mode. In the frequency comparison mode, the frequency comparator 7 compares the frequency of internal clock CLin (11), which is obtained by dividing the output frequency of the voltage controlled oscillator 5, with the frequency of external reference clock CLex (10). If the frequency of external reference clock CLex (10) is higher than the frequency of internal clock CLin (11), the frequency comparator 7 outputs an UP signal. If the frequency of external reference clock CLex (10) is lower than the frequency of internal clock CLin (11), the frequency comparator 7 outputs an DOWN signal. Receiving the UP signal or DOWN signal from the frequency comparator 7, the up/down counter 8 adds or subtracts “1” to/from the count value according to the received signal. Receiving a digital output of the up/down counter 8, the VCO characteristic control circuit 9 shifts the V-F (input voltage to frequency) characteristic of the voltage controlled oscillator 5 according to the value of the received digital output to change the output frequency. As a result, the frequency of internal clock CLin (11) increasingly or decreasingly changes to a frequency closer to that of external reference clock CLex (10).
The series of operations described above, i.e., a frequency comparison of external reference clock CLex (10) and internal clock CLin (11), change of the count value of the up/down counter 8 according to a result of the frequency comparison, and change of the V-F characteristic of the voltage controlled oscillator 5 by the VCO characteristic control circuit 9 such that the frequency of internal clock CLin (11) is changed to a frequency closer to that of external reference clock CLex (10), is repeated until these frequencies becomes substantially equal, and the frequency comparator 7 outputs frequency comparison stop signal FSTOP (16).
After the frequency comparator 7 outputs frequency comparison stop signal FSTOP (16), the count value of the up/down counter 8 is fixed, and the operation mode switch 3 switches from the F-side to the P-side, so that the output side of the charge pump 2 is connected to the input side of the loop filter 4. As a result, the loop changes to a phase comparison loop which passes through the phase comparator 1, the charge pump 2, the loop filter 4, the voltage controlled oscillator 5 and the frequency divider circuit 6.
In the phase comparison loop, the phase comparator 1 compares the phase of external reference clock CLex (10) with the phase of internal clock CLin (11). If the phase of external reference clock CLex (10) is faster than the phase of internal clock CLin (11), the phase comparator 1 outputs an UP signal for a time period corresponding to the phase difference. If the phase of external reference clock CLex (10) is slower than the phase of internal clock CLin (11), the phase comparator 1 outputs a DOWN signal for a time period corresponding to the phase difference. The charge pump 2 charges or discharges the loop filter 4 according to the UP signal or DOWN signal from the phase comparator 1. The loop filter 4 integrates the charging or discharging operation performed by the charge pump 2 and converts the integral to a direct voltage, which is employed as an input voltage to the voltage controlled oscillator 5. According to the input voltage, the output frequency of the voltage controlled oscillator 5 is changed. The series of operations described above is repeated until the phase of external reference clock CLex (10) and phase of internal clock CLin (11) are synchronized with each other, so that the output of the voltage controlled oscillator 5 is a signal (clock) which is synchronized with external reference clock CLex (10) and which has a frequency higher than that of external reference clock CLex (10) by a factor of N (N is the frequency dividing ratio of the frequency divider circuit 6).
Problems to be Solved
In the structure of the conventional dual loop PLL described above, the up/down counter 8 in the frequency comparison loop changes on a “1”-step by “1”-step basis. For example, when the maximum oscillation frequency is demanded in the voltage controlled oscillator 5, the count value of the up/down counter 8 must be changed to a maximum value. To this end, a frequency comparison in the frequency comparator 7 must be repeated 2M times (M is the number of bits of the up/down counter 8). Accordingly, the lock up time of the dual loop PLL increases.